Импульсные насосные преобразователи: магнитная интеграция и фильтры.

Импульсные насосные преобразователи: магнитная интеграция и фильтры.

Резюме

Pulsed fiber laser pump sources deliver 5 kW to 20 kW with sub-microsecond rise times, and their filters carry far more ripple current than the average load suggests. This article gives the integrated magnetics arithmetic, the pulsed capacitor stress equations, four field pain points, and five steps that hold output ripple under 1% in a 2 L/kW enclosure.

1. Введение

Pulsed fiber lasers for micromachining and semiconductor processing need pump sources that deliver 5 kW to 20 kW of peak power with rise times under 1 µs. Repetition rates run from 10 kHz to 500 kHz at 5% to 50% duty cycle.

That duty cycle changes the passive component problem. The magnetics must carry the peak current without saturating, the filter capacitors must hold a low impedance across three decades of frequency, and the whole assembly must fit 2 L to 5 L per kilowatt.

Conventional designs use three separate magnetic parts: the transformer, the output inductor, and the EMI choke. On a 5 kW pulsed source that set exceeds 1.5 L and 2 kg, which is 30% to 40% of the converter volume.

This article covers the integrated inductor-transformer concept, the pulsed current stress equations, four field pain points, and five design steps that pair an integrated core with N4700 Class I ceramic filtering.

2. Основной механизм

2.1 Integrated magnetics

A forward or flyback stage can carry the transformer and the output inductor on one core, using separate winding groups with a controlled leakage path. The primary sits on the centre leg and the secondary plus inductor windings sit on the outer legs.

The gap in the centre leg sets the leakage inductance that serves as the output filter choke:

l_gap = L_leakage × μ_0 × A_e / N_s²

where l_gap is the gap length, L_leakage the target filter inductance, μ_0 the permeability of free space, A_e the core cross-section, and N_s the secondary turns. A 5 µH target on a 2 cm² core with 10 secondary turns needs a 12.6 µm gap, so one core replaces three parts.

2.2 Pulsed current stress on the output capacitor

During the pulse on-time the capacitor supplies the load, and during the off-time it recharges. Its root-mean-square current follows the duty cycle:

I_C_rms = I_peak × √(D × (1 − D))

where I_C_rms is the capacitor ripple current, I_peak the pulse current, and D the duty cycle. At 100 A and 20% duty the ripple current is 40 A, which is twice the 20 A average load current.

That current dissipates in the bank resistance:

P_C = I_C_rms² × ESR

where P_C is the capacitor heating and ESR the equivalent series resistance. At 40 A the loss is 80 W for a 50 mΩ electrolytic bank, 8 W at the 5 mΩ of a single ceramic, and 0.4 W for a 20-part array at 0.25 mΩ combined.

2.3 Filter impedance and self-resonance

The filter must stay low impedance from DC to the highest harmonic of the pulse rate:

Z_filter(f) = √(ESR² + (2πfL − 1 / (2πfC))²)

where Z_filter is the impedance magnitude, f the frequency, L the equivalent series inductance, and C the bank capacitance. Below the self-resonant frequency the capacitive term dominates; above it the bank is inductive and the impedance climbs again.

The self-resonant frequency of a bank follows:

SRF = 1 / (2π × √(ESL × C))

where SRF is the self-resonant frequency, ESL the equivalent series inductance, and C the capacitance. A 10 µF bank with 10 nH of ESL resonates at 503 kHz, barely above the 100 kHz pulse rate, so the bank is already inductive at the second harmonic. Covering the band up to 10 MHz needs an array with combined ESL below 2 nH.

2.4 Core loss under pulsed drive

An integrated core carries both the transformer flux swing and the inductor flux swing, so its peak loss includes hysteresis and eddy current terms:

P_core = V_e × (k_hyst × f × B_peak^n + k_eddy × f² × B_peak²)

where P_core is the instantaneous core loss, V_e the core volume, k_hyst and k_eddy the loss coefficients, B_peak the peak flux density, and n the Steinmetz exponent.

At 20% duty the time-averaged loss is 0.2 × P_core. That 5× reduction lets the design run a higher B_peak during the pulse and shrink the core by 30% to 40%.

Fig. 1 — Capacitor ripple current peaks at 50 A near half duty, and a 100 A pulse train at 20% duty still pushes 40 A rms through the output bank.

3. Проблемы проектирования

Pain Point 1: 40 A rms through the output capacitor

A 100 A pulse at 20% duty puts 40 A rms through the output bank, twice the 20 A average load current. At 50 mΩ of electrolytic ESR that is 80 W of heat inside the capacitor.

The case temperature reaches 100 °C to 130 °C, the electrolyte evaporates, and capacitance falls 30% to 40% within 8,000 h. Lower capacitance raises the ripple, which raises the heating again, so the bank fails well before its rated life.

Pain Point 2: Pulse edge overshoot from ESL

The bank ESL converts the current ramp into a voltage spike: V_overshoot = ESL × I_peak / t_rise. A 20 nH bank with 100 A in 200 ns develops 10 V across the filter.

On a diode drive rail that spike is a large fraction of the signal, and it forward-biases junctions that should stay off. Holding the overshoot under 0.5 V at 100 A and 200 ns needs ESL below 1 nH.

Pain Point 3: DC bias loss in Class II ceramic filters

An X7R capacitor loses 20% to 50% of its nominal capacitance under DC bias. A 10 µF, 50 V part at 40 V of bias may measure only 5 µF to 7 µF.

Effective capacitance below nominal raises the filter impedance at the pulse repetition frequency, so the ripple grows. The loss also varies with temperature, which makes the filter design unpredictable across the operating range.

Pain Point 4: Core saturation on a fast load step

A 0 A to 100 A step in 200 ns drives the integrated core into saturation if the design leaves no margin above the peak current. Saturation drops the inductance toward zero and the current then rises without limit.

The diode array absorbs that current. Saturation current depends on the core material, the gap, and the winding arrangement, so check it against the worst-case transient, not the nominal pulse.

4. Этапы проектирования

Strategy 1: Build the filter from a matched ceramic array

Twenty 2.2 µF N4700 parts in parallel give 44 µF with 0.25 mΩ of combined ESR and 1.5 nH of combined ESL. Capacitor heating falls from 80 W to 0.4 W, which removes the liquid cooling requirement.

Overshoot then follows ESL × I_peak / t_rise = 1.5 nH × 100 A / 200 ns, or 0.75 V. A small damping resistor brings that inside the ±10% window of the drive rail.

Strategy 2: Use a dielectric with no DC bias loss

Class I ceramic holds its nominal capacitance at any DC bias, so a 2.2 µF part at 40 V still measures 2.2 µF, within ±0.35% over temperature. An X7R part of the same rating can fall to 1.1 µF.

That difference of 50% to 100% in effective capacitance lowers the filter impedance at the repetition frequency by 3 dB to 6 dB, and it holds across the whole thermal range.

Strategy 3: Set the leakage inductance with the core gap

Use an EE or PQ core with a controlled centre-leg gap. Put the primary on the centre leg and the secondary and inductor windings on the outer legs, then set l_gap from the filter inductance you need.

Combine the windings so the leakage path is set by the gap and not by the winding order. The part count falls from three magnetic components to one, and the reduced interconnect removes parasitic inductance that would otherwise sit in series with the filter.

Strategy 4: Pick a core material with low loss at the pulse rate

Choose MnZn ferrite with loss below 100 kW/m³ at 100 kHz and 200 mT. A 10 cm³ core then averages 0.2 W at 20% duty, which is small against the copper and capacitor losses.

Allow the peak flux density to rise during the pulse, since the average loss scales with duty. The same core then carries the same peak current in a smaller package, and the пленочный конденсатор across the input absorbs the step energy that the core cannot store. Hold the local bulk decoupling with HVCT8G parts so the array inductance stays low.

Strategy 5: Add local bypass, and rate the voltage on the pulse peak

Place 100 nF N4700 parts within 5 mm of the laser diode terminals with loop inductance below 2 nH. The bulk array covers 10 kHz to 500 kHz; the local parts cover 500 kHz to 10 MHz, so the filter holds low impedance across the full band.

Rate every capacitor on the peak pulse voltage, not the average. A 48 V rail with 10% transient overshoot reaches 52.8 V, so a 100 V part runs at 53% of rating with room for the long-term stress. Use быстровосстанавливающийся диод freewheel paths in the same loop so the recovery charge does not appear as a filter current step.

Параметр компонента	Типичное значение	Условие теста
Номинальное напряжение (серия HVCT8G)	10 кВ постоянного тока	высоковольтный режим 1.5× в течение 60 с
емкость	4700 пФ ±20% (472М)	1 МГц, 1 В среднеквадратичное значение
ЭПР на частоте 1 МГц	ниже 50 мОм	-
Индуктивность петли (хорда E40)	ниже 8 нГн	Расстояние между клеммами: 40 мм
сопротивление изоляции	сопротивление выше 10 ГОм при напряжении 500 В постоянного тока	25 ° C, 60% относительной влажности
Диапазон температур	от −40 °C до +125 °C	Серия МЭК 60068-2
Возможность импульсного DV/DT	выше 50 кВ/мкс	при номинальном напряжении

5. HVC N4700 capacitors for pulsed pump filters

Three requirements drive this node: ESR low enough for 40 A rms, inductance low enough for a 200 ns edge, and a capacitance that does not move under DC bias or temperature. HVC builds N4700 (T3M) Class I parts on a SrTiO3 base for that set, in a 6,000 m² owned factory in Dongguan, from 1 kV to 100 kV.

Шесть параметров, которые здесь имеют значение.

• ESR of 3 mΩ to 5 mΩ at 100 kHz, against 20 mΩ to 80 mΩ for electrolytics. At 40 A rms that is 4.8 W to 8 W per bank against 32 W to 128 W, which keeps a compact module on air cooling.
• No DC bias capacitance loss. Class I dielectric holds nominal capacitance at any bias, so the filter impedance at the pulse repetition frequency stays within ±0.35% of the design value, where X7R can lose 20% to 50%.
• Package inductance below 30 nH in the radial-lead HVCT8G outline. A 20-part array reaches 1.5 nH combined, which holds the overshoot on a 100 A, 200 ns edge at 0.75 V, and local bypass parts bring it below 0.5 V.
• Temperature coefficient of ±30 ppm/°C. Capacitance stays within ±0.35% from −55 °C to +125 °C, so the filter response does not follow the enclosure temperature.
• No aging drift. Capacitance stays within 2% after 50,000 h at 85 °C, with intrinsic life beyond 100,000 h, which is 5× to 10× the life of an electrolytic under the same pulsed current.
• Qualified as a drop-in for first-tier brands in field-repair programmes and specified by laser OEMs in new pulsed platforms. HVC parts match the electrical parameters and package dimensions of Murata высоковольтные компоненты винтового и радиального типов выводов.

Доставка и поддержка

Standard parts ship in 4–8 weeks, and matched custom sets in 6–10 weeks. HVC applications engineering supports pulsed current calculation, array design for minimum combined ESR and ESL, thermal analysis under pulsed load, and custom voltage and capacitance combinations.

Send the peak current, duty cycle, repetition rate, rise time, and rail voltage. HVC returns an array design with part numbers, combined ESR and ESL, and a two-sample evaluation kit within five working days.

6. Часто задаваемые вопросы

Q1: How much ripple current does a pulsed pump filter carry?

I_C_rms = I_peak × √(D × (1 − D)). At 100 A peak and 20% duty that is 40 A rms, twice the 20 A average load current. Size the bank on the RMS value, because heating follows I²R and the average current hides the real stress.

Q2: Why does an electrolytic output bank fail early here?

Because 40 A rms through 50 mΩ of ESR is 80 W inside the capacitor. Case temperature reaches 100 °C to 130 °C, capacitance falls 30% to 40% within 8,000 h, and the lower capacitance then raises both the ripple and the heating. A 44 µF N4700 array at 0.25 mΩ runs at 0.4 W.

Q3: What limits the pulse edge overshoot?

Bank ESL: V_overshoot = ESL × I_peak / t_rise. A 20 nH bank with 100 A in 200 ns develops 10 V. A 20-part ceramic array reaches 1.5 nH combined for 0.75 V, and 100 nF local bypass within 5 mm of the diode terminals brings it under 0.5 V.

Q4: Do I lose capacitance from DC bias in the filter?

With Class II ceramic, yes: an X7R part can lose 20% to 50% at rated bias, so a 10 µF, 50 V part at 40 V may measure 5 µF to 7 µF. Class I N4700 holds nominal capacitance at any bias and stays within ±0.35% over temperature, which lowers the filter impedance by 3 dB to 6 dB at the repetition rate.

Q5: How does magnetic integration cut volume?

One gapped core carries the transformer, the output inductor, and the EMI choke. l_gap = L_leakage × μ_0 × A_e / N_s² sets the filter inductance, so a 5 µH target on a 2 cm² core with 10 secondary turns needs a 12.6 µm gap. Three magnetic parts become one.

Q6: What core material suits a 20% duty pulse train?

MnZn ferrite with loss below 100 kW/m³ at 100 kHz and 200 mT. Average loss scales with duty, so a 10 cm³ core runs near 0.2 W at 20% duty. That 5× reduction against continuous operation lets the peak flux density rise and the core shrink by 30% to 40%.

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